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march 2013 docid18265 rev 8 1/25 AN3319 application note steval-isv006v2: solar battery charger using the spv1040 introduction the spv1040 is a high efficiency, low power and low voltage dc-dc converter that provides a single output voltage up to 5.2 v. startup is guaranteed at 0.3 v and the device operates down to 0.45 v when coming out from mppt mode. it is a 100 khz fixed frequency pwm step-up (or boost) converter able to maximize the energy generated by few solar cells (polycrystalline or amorphous). the duty cycle is controlled by an embedded unit running an mppt algorithm with the goal of maximizing the power generated from the panel by continuously tracking its output voltage and current. the spv1040 guarantees the safety of overall application and of converter itself by stopping the pwm switching in the case of an overcurrent or overtemperature condition. the ic integrates a 120 m n-channel mosfet power switch and a 140 m p-channel mosfet synchronous rectifier. www.st.com
contents AN3319 2/25 docid18265 rev 8 contents 1 application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 boost switching application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 spv1040 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 schematic and bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 external component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 optional schottky . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 appendix a spv1040 parallel and series connection . . . . . . . . . . . . . . . . . . . . . 20 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
docid18265 rev 8 3/25 AN3319 list of figures list of figures figure 1. boost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. pv cell curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. inductor current in continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. inductor current in discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. typical application schematic using the spv1040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. spv1040 equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. mppt working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. spv1040 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. steval-isv006v2 top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 10. steval-isv006v2 bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 figure 11. steval-isv006v2 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. steval-isv006v2 iout filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. steval-isv006v2 pcb top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 14. steval-isv006v2 pcb bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 15. spv1040 output parallel connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 16. spv1040 output series connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
application overview AN3319 4/25 docid18265 rev 8 1 application overview figure 1 shows the typical architecture of a boost converter based solar battery charger: figure 1. boost application schematic the spv1040 adapts the characteristics of load to those of panel. in fact, a pv panel is made up of a series of pv cells. each pv cell provides voltage and current which depend on the pv cell size, on its technology, and on the light irradiation power. the main electrical parameters of a pv panel (typically provided at light irradiation of 1000 w/m 2 , t amb =25 c) are: ? v oc (open circuit voltage) ? v mp (voltage at maximum power point) ? i sc (short-circuit current) ? i mp (current at maximum power point) figure 2 shows the typical characteristics of a pv cell: figure 2. pv cell curve mpp (maximum power point) is the working point of the pv cell at which the product of the extracted voltage and current provides the maximum power. $0y $0y , , 6& , 03 u uhqw>$@ z hu>:@ &x u 3r z 9rowd j h > 9 @ 9 2& 9 03 j>@
docid18265 rev 8 5/25 AN3319 boost switching application 2 boost switching application a step-up (or boost) converter is a switching dc-dc converter able to generate an output voltage higher than (or at least equal to) the input voltage. referring to figure 1 , the switching element (s w ) is typically driven by a fixed frequency square waveform generated by a pwm controller. when s w is closed (t on ) the inductor stores energy and its current increases with a slope depending on the voltage across the inductor and its inductance value. during this time the output voltage is sustained by c out and the diode does not allow any charge transfer from the output to input stage. when s w is open (t off ), the current in the inductor is forced, flowing toward the output until voltage at the input is higher than the output voltage. during this phase the current in the inductor decreases while the output voltage increases. figure 3 shows the behavior of inductor current. figure 3. inductor current in continuous mode the energy stored in the inductor during t on is ideally equal to the energy released during t off , therefore the relation between t on and t off can be written as follows: where ?d? is the duty cycle of the square waveform driving the switching element. boost applications can work in two different modes depending on the minimum inductor current within the switching period, that is if it is not null or null respectively: ? continuous mode (cm) ? discontinuous mode (dcm) $0y , /; , /[sn / 9 / , /[plq ( rq ( rii wlph w rq w rii ( rq ( rii ,1 9 ,1 9 287 d t on t on t off + () -------------------------- =
boost switching application AN3319 6/25 docid18265 rev 8 figure 4. inductor current in discontinuous mode obviously the efficiency is normally higher in cm. inductance and switching frequency (f sw ) impact the working mode. in fact, in order to have the system working in cm, the rule below should be followed: according to the above, l is minimum for d = 50 %. $0y , /[ , /[sn ( rq ( rii / / w rq w rii w lgoh wlph 9 9 287 ,1 9 ,1 l v out p in -------------- d1d ? () ? () 2 2f sw ? ---------------------------------- - ? > 2
docid18265 rev 8 7/25 AN3319 spv1040 description 3 spv1040 description the following is a quick overview of spv1040 functions, features, and operating modes. figure 5. typical application schematic using the spv1040 the spv1040 acts as an impedance adapter between the input source and output load which is: figure 6. spv1040 equivalent circuit through the mppt algorithm, it sets up the dc working point properly by guaranteeing z in = z m (assuming z m is the impedance of the supply source). in this way, the power extracted from the supply source (p in = v in * i in ) is maximum (p m = v m * i m ). the voltage-current curve shows all the available working points of the pv panel at a given solar irradiation. the voltage-power curve is derived from the voltage-current curve by plotting the product v*i for each voltage generated. am06700v1 lx r s l v batt xshut gnd mpp set v pv r 1 r 3 c out r f1 r f2 c f mpp - set r 2 c insns c outsns c in d out i ctrl_minus i ctrl_plus v ctrl v out $0y 639 , , 5 & , 9 9 jp9 & , = '& 5 9 9 39 3dqho */ */ */ */ 065 065 065 065
spv1040 description AN3319 8/25 docid18265 rev 8 figure 7. mppt working principle figure 7 shows the logical sequence followed by the device which proceeds for successive approximations in the search for the mpp. this method is called ?perturb and observe?. the diagram shows that a comparison is made between the digital value of the power pn generated by the solar cells and sampled at instant n, and the value acquired at the previous sampling period pn-1. this allows the mppt algorithm to determine the sign of duty cycle and to increment or decrement it by a predefined amount. in particular, the direction of adjustment (increment or decrement of duty cycle) remains unchanged until condition pn pn-1 occurs, that is, for as long as it registers an increase of the instantaneous power extracted from the cells string. on the contrary, when it registers a decrease of the power pn$@ >:@ xuuhq w r zhu & 3 r 9rowdjh>9@ 9 2& 9 03 am06703v1 lx start signal zero crossing + analog block start signal vref + - zero crossing detector v mpp-ref xshut - burst ref clock over current over temperature reverse polarity drivers control mpp-set + - mpp-set v mpp-ref mpp block clock burst mode dac code digital core pwm gnd + - vref iout reg vin reg vout reg - i ctrl_minus i ctrl_plus v ctrl v out
docid18265 rev 8 9/25 AN3319 spv1040 description the duty cycle set by the mppt algorithm can be overwritten if one of the following is triggered: ? overcurrent protection (ovc), peak current on low side switch 1.8 a ? overtemperature protection (ovt), internal temperature 155 c ? output voltage regulation, v ctrl pin triggers 1.25 v ? output current regulation r s * (i ctrl_plus - i ctrl_minus ) 50 mv ? mpp-set voltage v mpp-set 300 mv at the start-up and v mpp-set 450 mv in working mode. application components must be carefully selected to avoid any undesired trigger of the above thresholds. in order to improve the overall system efficiency, and to reduce the bom, the spv1040 also integrates a zero crossing block whose role is to turn-off the synchronous rectifier to prevent reverse current flowing from output to input.
application example AN3319 10/25 docid18265 rev 8 4 application example figure 9 and 10 show the demonstration board of a solar battery charger based on spv1040 and on a status of charge indication circuit. figure 9. steval-isv006v2 top view figure 10. steval-isv006v2 bottom view steval-isv006v2 has been designed to recharge any type of battery (except lithium compound) which maximum voltage (v batt_max ) 5.2 v and supplied by up to 5 w pv panels (constrained by v oc docid18265 rev 8 11/25 AN3319 application example further, steval-isv006v2 provides a simple charge status circuit with 2 leds: ? red led on and green led off, if the battery voltage is lower than charge threshold ? red led off and green led on, if the battery voltage is higher than charge threshold charge threshold can be regulated by trimmer vr 10 . charge status circuit can be bypassed by opening jumper j1.
schematic and bill of material AN3319 12/25 docid18265 rev 8 5 schematic and bill of material figure 11. steval-isv006v2 schematic ta ble 1 shows the list of external components used in the demonstration board. am06706v1 v bat+ optional lx r s1 pv+ l1 x j 1 battery charge monitor circuit xshut gnd mpp set r 1 r 3 r f1 r f2 c f x shut r 5 v load+ super cap v r 10 mpp - set vr 2 vr 4 ( dnm ) c 4 c 2 c in1 d out pv- c out2 r 11 v load - r 9 c out1 load v bat- i ctrl_minus i ctrl_plus v out v ctrl table 1. bom c o m p o n e n t (alternate label) name value supplier serial number u25/26 solar battery charger stmicroelectronics spv1040t pv panel poly-crystalline pv panel 200 mw nbszgd szgd7050-3p cin1 input capacitor 10 f epcos c2012x5r1a106k c4 voltage sensing capacitor 100 nf epcos c2012x5r1h104k c2 voltage sensing capacitor 1 nf epcos c2012c0g1h102j cout1 output capacitor 4.7 f epcos c2012x5r0j475k cout2 output capacitor 10 f epcos c2012x5r1a106k r3 input voltage partitioning resistor 1 k cyntec rg2012p1001bn vr2, vr10 vr4 (dnm) out, mpp-set and charge indication partitioning resistor 0-1 mk vishay 63m-105 r1 output voltage partitioning resistor 1 m cyntec rg2012p105bn r11 output voltage partitioning resistor 330 k cyntec rg2012p334bn r5 pull-up resistor 0 cyntec rl1220tr010fn
docid18265 rev 8 13/25 AN3319 schematic and bill of material l1 inductor 10 h coilcraft coilcraft epcos xal6060-103 mss7341-103 b82442t1103k050 j28 super capacitor 220 nf panasonic eecs0hd224h dout1 protection diode stmicroelectronics smm4f5.0 rs1 output current sense 10 m cyntec rl1220tr000fn rf1, rf2 noise filterirng resistors 1 k cyntec rg2012p1001bn cf1 noise filtering capacitor 1 f epcos c2012x7r1c105k u27 quad comparator stmicroelectronics ts339 d1 green led 1.8 v, 2 ma avago tech. hlmp-1790 d4 red led 1.8 v, 2 ma avago tech. hlmp-1700 d5 reference diode stmicroelectronics stps160u r6, r7 led protection resistors 1 k cyntec rg2012p1001bn r8 reference resistors 1 m cyntec rg2012p105bn r9 charge status threshold resistors 27 k cyntec rg2012p2701bn table 1. bom (continued) c o m p o n e n t (alternate label) name value supplier serial number
external component selection AN3319 14/25 docid18265 rev 8 6 external component selection spv1040 requires a set of external components and their proper selection guarantees both the best chip functionality and system efficiency. input voltage capacitor c in is the input capacitor connected to the input rail in order to reduce the voltage ripple. according to the maximum current (i sc ) provided by the pv panel connected at the input, the following formula should be considered to select the proper capacitance value for a specified maximum input voltage ripple (v in_rp_max ): maximum voltage of this capacitor is strictly dependent on the input source (typically between 1 v and 3 v). low-esr capacitors are a good choice to increase the whole system efficiency. in order to reduce the esr effect, it is suggested to split the input capacitance into two capacitors placed in parallel. input voltage partitioning v mpp-set is the pin used to monitor the voltage generated by the solar cells. the v mpp-set pin can be directly connected to pv+ rail through a 1 k r 3 resistor. with regard to the v mpp-set pin, two constraints must be taken into account: ? when spv1040 is off, v mpp-set voltage must be 0.3 to turn-on the device ? when spv1040 is in operating mode, it enters burst mode if v mpp-set decreases triggering the 450 mv threshold. input voltage sensing capacitor c 4 is placed as close as possible to the v mpp-set pin to reject noise on v mpp-set voltage. however, v mpp-set must be able to follow the v in waveform to allow spv1040 to monitor input voltage variations. it means that the time constant r 3 *c 4 must be chosen according to system properties, which is the mppt tracking time (t mpp ? 1 ms). the rule below must be followed in order to select c 4 capacitance: assuming r 3 = 1 k then: c in i sc f sw v in ? ------------------------- _rp_max c 4 t mpp 1 r 3 ------ - 10 3 ? 1 10 3 -------- - ? = ? f
docid18265 rev 8 15/25 AN3319 external component selection inductor selection inductor selection is a crucial point for this application. the following application constraints must be taken into account: ? maximum input current (i.e. i mp and i sc of pv panel) ? maximum input voltage (i.e. v mp and voc of pv panel) ? overcurrent threshold of spv1040 (1.8 a) ? maximum duty cycle of spv1040 (90 %). the input current from the pv panel flows into the inductor, so: according to figure 3 , during the charge phase (switch on), peak current on the inductor depends on the applied voltage (v in ) on the inductance (l x ), and on the duty cycle (t on ). considering the maximum duty cycle (90 %): taking into account the overcurrent threshold: finally, inductance should be chosen according to the following formula: a safer choice is to replace v mp with v oc . usually, inductances ranging between 10 h to 100 h satisfy most application requirements. other critical parameters for the inductor choice are irms, saturation current, and size. irms is the self rising temperature of the inductor, affecting the nominal inductance value. in particular, the inductance decreases with irms and the temperature increases. as a consequence the inductor current peak can reach or surpass 1.8 a. inductor size also affects the maximum current deliverable to the load. in any case, the saturation current of the choke should be higher than the peak current limit of the input source. hence, the suggested saturation current must be > 1.8 a. at the same size, small inductance values guarantee both faster response to load transients and higher efficiency. inductors with low series resistance are suggested in order to guarantee high efficiency. output voltage capacitor a minimum output capacitance must be added at the output in order to reduce the voltage ripple. critical parameters for capacitors are: capacitance, maximum voltage, and esr. i lxrms i mp i sc < ? ? v mp ? 2l x ------------------------------- + = i lxpeak 1.8a < -- - 910 6 ? v mp ? 2i lxrms ? ------------------------------- 1 2 -- - 910 6 ? v mp ? 2i mp ? ------------------------------- ? = ? >
external component selection AN3319 16/25 docid18265 rev 8 according to the maximum current (i sc ) provided by the pv panel connected at the input, the following formula can be used to select the proper capacitance value (c out ) for a specified maximum output voltage ripple (v out_rp_max ): maximum voltage of this capacitor is strictly dependent on the output voltage range. spv1040 can support up to 5.2 v, so the suggested maximum voltage for these capacitors is 10 v. low-esr capacitors are a good choice to increase the whole system efficiency. output voltage partitioning r 1 and r 2 are the two resistors used for partitioning the output voltage. the said v out_max the maximum output voltage of the battery, r 1 and r 2 must be selected according to the following rule: also, in order to optimize the efficiency of the whole system, when selecting r 1 and r 2 , their power dissipation must be taken into account. assuming a negligible current flowing into the v ctrl pin, maximum power dissipation on the series r 1 +r 2 is: as an empirical rule, r 1 and r 2 should be selected to get: note: in order to guarantee proper functionality of the v ctrl pin, the current flowing into the series r 1 +r 2 should be in the range between 2 a and 20 a. output voltage sensing capacitor c 2 is placed in parallel to r 2 and as close as possible to the v ctrl pin. its role is to reject the noise on the voltage sensed by the v ctrl pin. capacitance value depends on the time constant resulting from r 2 ( out = c 2 *r 1 //r 2 ) and from the system switching frequency (100 khz), as follows: c out i sc f sw v ? ------------------- - out_rp_max r 1 r 2 ------ - v out 1.25 -------------- = _max -1 p vctrl _sns v outmax () 2 r 1 r 2 + ------------------------------- - = _ p vctrlsns 0.01 v outmax i outmax ? () ? ? _ _ _ ssw f 1 10 out ? ? 2 1 ssw 2 r // r 1 * f 1 * 10 c ?
docid18265 rev 8 17/25 AN3319 external component selection output current sensing filter r s is placed in the output rail between the i ctrl_minus and i ctrl_plus pins. its role is to sense the output current (i out ) flowing toward the load. voltage drop on r s is sensed by the i ctrl_minus and i ctrl_plus pins and compared with the 50 mv internal threshold. the triangular waveform of the current and noise may cause unexpected triggering of the 50 mv threshold. this can be avoided with a filter such as the one shown below: figure 12. steval-isv006v2 i out filter suggested values are: r f1 =r f2 = 1 k c f = 1 f output protection diode if the load is not a battery, d out is required and placed in parallel to the output load. its role is to protect the devices in case a pv cell providing i mp > 0.5 a is connected when very low load is connected. in fact, spv1040 is supplied by the v out pin, so in the above condition the device is still off when the pv cell is connected and a voltage spike can occur damaging the converter and the battery. in order to guarantee the best system performance and reliability, d out should be selected as follows: v br > v out_max v cl 5.5 v d out must be able to dissipate the following maximum power: p max = i sc *v cl xshut resistor the xshut pin controls spv1040 turn-on (0.3 v xshut 5.2 v) or turn-off (xshut < 0.3 v). r s 50mv i outmax --------------------- - ? _ am06707v1 r s r f1 r f2 c f v out i ctrl_plus i ctrl_minus bat+ v
external component selection AN3319 18/25 docid18265 rev 8 r 5 is a 0 pull-up resistor shorting the xshut and mpp-set pins. removing r5 enables the external control of the xshut pin to turn the spv1040 on/off. 6.1 optional schottky an external schottky diode between l x and v out pins is mandatory in all the applications with v batt_max > 4.8 v. in fact, voltage on l x pin can go above the maximum absolute voltage threshold (5.5 v) due to the voltage drop on the high side integrated switch when this is off (discontinuous mode) and current needs to flow from input to output. this schottky diode should be chosen according to the following criteria: for setting up the application and simulating the related test results please go to www.st.com/edesignstudio. v f 5.5v batt_max and i f i lmax v -
docid18265 rev 8 19/25 AN3319 layout 7 layout figure 13. steval-isv006v2 pcb top view figure 14. steval-isv006v2 pcb bottom view layout guidelines pcb layout is very important in order to minimize voltage and current ripple, high frequency resonance problems, and electromagnetic interference. it is essential to keep the paths where the high switching current circulates as small as possible in order to reduce radiation and resonance problems. large traces for high current paths and an extended ground plane reduce noise and increase efficiency. the output and input capacitors should be placed as close as possible to the device. the external resistor dividers, if used, should be as close as possible to the v mpp-set and v ctrl pins of the device, and as far as possible from the high current circulating paths, in order to avoid picking up noise.
spv1040 parallel and series connection AN3319 20/25 docid18265 rev 8 appendix a spv1040 parallel and series connection output pins of many spv1040s can be connected either in parallel or in series. in both cases the output power (pout) depends on light irradiation of each panel, on application efficiency, and on the specific constraints of the selected topology. the objective of this section is to explain how the output power is impacted by the selected topology. an example with 3 pv panels (panel1, panel2, panel3) is presented, but the conclusion can be extended to a larger number of pv panels. if the panel is lighted and the spv1040 is on (it means that light irradiation intensity is such that v mpp-set 0.3 v): if the panel is completely shaded: p outx =0 spv1040 parallel connection this topology guarantees the desired output voltage even when only one panel is irradiated. the obvious constraint of this topology is that v out is limited to the spv1040 maximum output voltage. figure 15 shows the parallel connection topology: figure 15. spv1040 output parallel connection the output partitioning (r 1 /r 2 ) of each spv1040 must be coherent with the desired v outx . according to the topology: v out =v out1 =v out2 =v out3 i out =i out1 +i out2 +i out3 ] 3 .. 1 x [ = p inx = am06711v1 pv3 spv1040 vo3+ vo3- pv3+ pv3- pv2 spv1040 vo2+ pv2+ pv2 pv1 vo2- pv2 - spv1040 vo1+ pv1+ spv1040 vo1- pv1- out+ v out- v
docid18265 rev 8 21/25 AN3319 spv1040 parallel and series connection according to the light irradiation on each panel and to the system efficiency ( ), the output power results: therefore: each spv1040 contributes to the output power providing i outx . finally, the desired v out is guaranteed if at least one of the 3 pv panels provides enough power to turn-on the spv1040 relating to it. spv1040 series connection this topology provides an output voltage that is the sum of the output voltages of the spv1040 connected in series. the objective of this section is to explain how the output power is impacted by the selected topology. figure 16 shows the series connection topology: figure 16. spv1040 output series connection in this case, the topology imposes: in case irradiation is the same for each panel: ] 3 .. 1 x [ = ] 3 .. 1 x [ = 3 out 2 out 1 out out p p p p + + = outx outx outx i * v p = inx inx inx i * v p = 3 in 2 in 1 in 3 out 2 out 1 out out out p p p ) i i i ( v p + + = + + = am06710v1 pv3 spv1040 vo3+ vo3- pv3+ pv3- pv2 spv1040 vo2+ pv2+ pv2 pv1 vo2- pv2 - spv1040 vo1+ pv1+ spv1040 vo1- pv1- out+ v out- v 3 out 2 out 1 out out i i i i = = = 3 out 2 out 1 out out v v v v + + = ] 3 .. 1 x [ = 3 out 2 out 1 out p p p = = outx out p * 3 p = out outx p 3 1 p = out 1 out outx outx outx i * v i * v p = =
spv1040 parallel and series connection AN3319 22/25 docid18265 rev 8 therefore: for example, assuming p out = 3 w and v out = 12 v, then v outx = 4 v. lower irradiation for one panel, for example on panel 2, causes lower output power, so lower v out2 due to the i out imposed by the topology: the output voltage required by the load can be provided by the 1 st and the 3 rd spv1040 but only up to the limit imposed by each of their r 1 /r 2 partitionings. some examples can help in understanding the various scenarios assuming that each r 1 /r 2 limits v outx to 4.8 v. example 1: panel 2 has 75 % irradiation of panels 1 and 3: two spv1040s (1 st and 3 rd ) supply the voltage drop caused by the lower irradiation on panel 2. warning: spv1040 is a boost controller, so v outx must be higher than v inx , otherwise the spv1040 turns off and the input power is transferred to the output stage through the integrated p- channel mos without entering the switching mode. out outx v 3 1 v = out outx outx i p v = 3 ou t 1 out 2 out v * 4 3 v * 4 3 v = = w 1 p p 3 out 1 out = = w 75 . 0 p 4 3 p 1 ou t 2 out = = w 75 . 2 p p p p 3 out 2 out 1 out out = + + = a 23 . 0 12 75 . 2 v p i out out out = = = v 35 . 4 23 . 0 1 v v 3 out 1 out = = = v 26 . 3 23 . 0 75 . 0 v 2 out = =
docid18265 rev 8 23/25 AN3319 spv1040 parallel and series connection example 2: panel 2 has 50 % irradiation of panels 1 and 3: in this case the system is close to its maximum voltage limit, in fact, a lower irradiation on panel 2 impacts v out1 and/or v out3 which are very close to the maximum output voltage threshold (4.8 v) imposed by r 1 /r 2 partitioning. example 3: panel 2 completely shaded. in this case the maximum v out can be 9.6 v (v out1 +v out3 ). the current flow is guaranteed by the body diodes of the power mosfets integrated in the spv1040 (or by the bypass diodes, if any, placed between v out- and v out+ ). p out1 p out3 1w == p out2 1 2 -- - p out1 1 2 -- - p out3 ? = ? = p out2 1 2 -- - p out1 0.5w == p out p out1 p out2 p out3 2.5w = ++ = i out p out v out -------------- 2.5 12 ------- - 0.21a = = = v out1 v out3 1 0.21 ----------- 4.76v = = = v out2 0.5 0.21 ----------- 2.38v = =
revision history AN3319 24/25 docid18265 rev 8 revision history table 2. document revision history date revision changes 02-feb-2011 1 initial release 18-apr-2011 2 ? demonstration board changed: from steval-isv006v1 to steval-isv006v2 ? figure 9 , 10 , 11 , 13 and 14 modified ? section 4 modified ? table 1 modified 04-may-2011 3 modified: table 1 08-sep-2011 4 ? modified: section 3 and 4 ? changed: table 1: bom ? changed: figure 5 , 8 , 9 and 11 ? modified: input voltage partitioning , input voltage sensing capacitor 12-sep-2011 5 minor text changes 21-sep-2011 6 ? modified: figure 5 , 8 and 11 ? modified: text and equation for input voltage sensing capacitor in section 6: external component selection 18-nov-2011 7 modified: value of the component rs1 in table 1 21-mar-2013 8 updated figure 8 .
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